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PLL Frequency Synthesizer ADF4106
FEATURES 6.0 GHz Bandwidth 2.7 V to 3.3 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 3 V Systems Programmable Dual-Modulus Prescaler 8/9, 16/17, 32/33, 64/65 Programmable Charge Pump Currents Programmable Antibacklash Pulsewidth 3-Wire Serial Interface Analog and Digital Lock Detect Hardware and Software Power-Down Modes APPLICATIONS Broadband Wireless Access Instrumentation Wireless LANs Base Stations for Wireless Radio GENERAL DESCRIPTION
The ADF4106 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phaselocked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and lowering cost.
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP CPGND RSET REFERENCE
REFIN
14-BIT R COUNTER
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CP
14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER 22 FUNCTION LATCH CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 LOCK DETECT CURRENT SETTING 1 CURRENT SETTING 2
FROM FUNCTION LATCH
AB COUNTER LATCH
HIGH Z 19 13 AVDD MUX MUXOUT
N = BP + A 13-BIT B COUNTER LOAD RFINA RFINB PRESCALER P/P + 1 LOAD 6-BIT A COUNTER
SDOUT
M3 M2 M1
ADF4106
6
REV. A
CE
AGND
DGND
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DV V 10%; V; R ; = T to , unless otherwise ADF4106-SPECIFICATIONS1 (AV ==5.1 k =; 3dBm referredAVto 50V T5.5 V; AGNDT= DGND = CPGND = 0noted.)
DD DD DD P SET A MIN MAX
Parameter RF CHARACTERISTICS RF Input Frequency (RFIN)3 RF Input Sensitivity Maximum Allowable Prescaler Output Frequency4 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity5 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency6 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD7 (AIDD + DIDD) IP Power-Down Mode8 (AIDD + DIDD)
B Version 0.5/6.0 -10/0 300 20/250 0.8/AVDD 10 100 56
1
BChips2 (Typ) 0.5/6.0 -10/0 300 20/250 0.8/AVDD 10 100 56
Unit GHz min/max dBm min/max MHz max MHz min/max V p-p min/max pF max A max MHz max
Test Conditions/Comments See Figure 3 for Input Circuit
For f < 20 MHz, Use DC-Coupled Square Wave (0 to VDD) AC-Coupled; When DC-Coupled, 0 to VDD max (CMOS Compatible)
5 625 2.5 2.7/10 1 2 1.5 2 1.4 0.6 1 10 1.4 VDD - 0.4 100 0.4 2.7/3.3 AVDD AVDD/5.5 15 0.4 10
5 625 2.5 2.7/10 1 2 1.5 2 1.4 0.6 1 10 1.4 VDD - 0.4 100 0.4 2.7/3.3 AVDD AVDD/5.5 13 0.4 10
mA typ A typ % typ k typ nA typ % typ % typ % typ V min V max A max pF max V min V min A max V max V min/V max V min/V max mA max mA max A typ
Programmable, See Table V With RSET = 5.1 k With RSET = 5.1 k See Table V 0.5 V VCP 0.5 V VCP VCP = VP/2 VP - 0.5 V VP - 0.5 V
Open-Drain Output Chosen 1 k Pull-up to 1.8 V CMOS Output Chosen IOL = 500 A
AVDD VP 13 mA typ TA = 25C
5.5 V
-2-
REV. A
ADF4106
Parameter NOISE CHARACTERISTICS ADF4106 Phase Noise Floor9 Phase Noise Performance10 900 MHz Output11 5800 MHz Output12 5800 MHz Output13 Spurious Signals 900 MHz Output11 5800 MHz Output12 5800 MHz Output13 B Version -174 -166 -159 -93 -74 -84 -90/-92 -65/-70 -70/-75
1
BChips2 (Typ) -174 -166 -159 -93 -74 -84 -90/-92 -65/-70 -70/-75
Unit dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc typ dBc typ dBc typ
Test Conditions/Comments @ 25 kHz PFD Frequency @ 200 kHz PFD Frequency @ 1 MHz PFD Frequency @ VCO Output @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 1 MHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 1 MHz/2 MHz and 1 MHz PFD Frequency
NOTES 1 Operating temperature range (B Version) is -40C to +85C. 2 The BChip specifications are given as typical values. 3 Use a square wave for lower frequencies, below the mimimum stated. 4 The maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 5 AVDD = DVDD = 3 V. 6 Guaranteed by design. Sample tested to ensure compliance. 7 TA = 25C; AVDD = DVDD = 3 V; P = 16; RF IN = 6.0 GHz. 8 TA = 25C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RF IN = 6.0 GHz. 9 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 10 The phase noise is measured with the EVAL-ADF4106EB1 evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REF IN for the synthesizer (f REFOUT = 10 MHz @ 0 dBm). 11 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 29000; Loop B/W = 20 kHz. 13 fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; f RF = 5800 MHz; N = 5800; Loop B/W = 100 kHz. Specifications subject to change without notice.
TIMING CHARACTERISTICS
Parameter t1 t2 t3 t4 t5 t6
(AVDD = DVDD = 3 V 10%; AVDD VP 5.5 V; AGND = DGND = CPGND = 0 V; RSET = 5.1 k ; TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN to TMAX (B Version) 10 10 25 25 10 20
Unit ns min ns min ns min ns min ns min ns min
Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth
NOTES Guaranteed by design but not production tested. Specifications subject to change without notice.
t3
CLOCK
t4
t1
DATA DB23 (MSB) DB22
t2
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE
t5
LE
Figure 1. Timing Diagram
REV. A
-3-
ADF4106
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C, unless otherwise noted.)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3.6 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.8 V VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.8 V Digital I/O Voltage to GND . . . . . . . . -0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . . -0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150C TSSOP JA Thermal Impedance . . . . . . . . . . . . . . 150.4C/W
LFCSP JA Thermal Impedance . . . . . . . . . . . . . . . . 122C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V.
ORDERING GUIDE
Model ADF4106BRU ADF4106BRU-REEL ADF4106BRU-REEL7 ADF4106BCP ADF4106BCP-REEL ADF4106BCP-REEL7 EVAL-ADF4106EB1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Option* RU-16 RU-16 RU-16 CP-20 CP-20 CP-20
*RU = Thin Shrink Small Outline Package (TSSOP). CP = Lead Frame Chip Scale Package (LFCSP). Contact the factory for chip availability. Note that aluminum bond wire should not be used with the ADF4106 die.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4106 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-4-
REV. A
ADF4106
PIN CONFIGURATIONS TSSOP
RSET 1 CP 2 CPGND 3 AGND 4
16 15 14
LFCSP
VP DVDD MUXOUT LE CPGND 1 AGND 2 AGND 3 RFINB 4 RFINA 5
PIN 1 INDICATOR
20 CP 19 RSET 18 VP 17 DVDD 16 DVDD
ADF4106
13
TOP VIEW RFINB 5 (Not to Scale) 12 DATA RFINA 6 AVDD 7 REFIN 8
11 10 9
ADF4106
TOP VIEW
CLK CE DGND
15 MUXOUT 14 LE 13 DATA 12 CLK 11 CE
NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR)
PIN FUNCTION DESCRIPTIONS
Mnemonic RSET
Function Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is
ICP MAX =
25.5 RSET
CP CPGND AGND RFINB RFINA AVDD REFIN DGND CE CLK DATA LE MUXOUT DVDD VP
So, with RSET = 5.1 k, ICP MAX = 5 mA. Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 3. Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 k. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high powers up the device, depending on the status of the power-down bit F2. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the 2 LSB being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
REV. A
-5-
AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10
ADF4106-Typical Performance Characteristics
FREQ UNIT - GHz PARAM TYPE - S DATA FORMAT - MA
KEYWORD - R IMPEDANCE - 50
-40 -50 10dB/DIV RL = -40dBc/Hz RMS NOISE = 0.36
FREQ 0.500 0.600 0.700 0.800 0.900 1.000 1.100 1.200 1.300 1.400 1.500 1.600 1.700 1.800 1.900 2.000 2.100 2.200 2.300 2.400 2.500 2.600 2.700 2.800 2.900 3.000 3.100 3.200
MAGS11 0.89148 0.88133 0.87152 0.85855 0.84911 0.83512 0.82374 0.80871 0.79176 0.77205 0.75696 0.74234 0.72239 0.69419 0.67288 0.66227 0.64758 0.62454 0.59466 0.55932 0.52256 0.48754 0.46411 0.45776 0.44859 0.44588 0.43810 0.43269
ANGS11 - 17.2820 - 20.6919 - 24.5386 - 27.3228 - 31.0698 - 34.8623 - 38.5574 - 41.9093 - 45.6990 - 49.4185 - 52.8898 - 56.2923 - 60.2584 - 63.1446 - 65.6464 - 68.0742 - 71.3530 - 75.5658 - 79.6404 - 82.8246 - 85.2795 - 85.6298 - 86.1854 - 86.4997 - 88.8080 - 91.9737 - 95.4087 - 99.1282
FREQ 3.300 3.400 3.500 3.600 3.700 3.800 3.900 4.000 4.100 4.200 4.300 4.400 4.500 4.600 4.700 4.800 4.900 5.000 5.100 5.200 5.300 5.400 5.500 5.600 5.700 5.800 5.900 6.000
MAGS11 0.42777 0.42859 0.43365 0.43849 0.44475 0.44800 0.45223 0.45555 0.45313 0.45622 0.45555 0.46108 0.45325 0.45054 0.45200 0.45043 0.45282 0.44287 0.44909 0.44294 0.44558 0.45417 0.46038 0.47128 0.47439 0.48604 0.50637 0.52172
ANGS11 - 102.748 - 107.167 - 111.883 - 117.548 - 123.856 - 130.399 - 136.744 - 142.766 - 149.269 - 154.884 - 159.680 - 164.916 - 168.452 - 173.462 - 176.697 178.824 174.947 170.237 166.617 162.786 158.766 153.195 147.721 139.760 132.657 125.782 121.110 115.400
-60 PHASE NOISE - dBc/Hz -70 -80 -90 -100 -110 -120 -130 -140 100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
TPC 1. S-Parameter Data for the RF Input
TPC 4. Integrated Phase Noise (900 MHz, 200 kHz, and 20 kHz)
0 VDD = 3V VP = 3V -5
0
REF LEVEL = -14.0dBm
-10 -20
OUTPUT POWER - dB
OUTPUT POWER - dB
-10
-30 -40 -50 -60 -70 -80
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 30
-15
-20
TA = +85 C
-25
-91.0dBc/Hz
TA = +25 C TA = -40 C
-90
5 6
-30
0
1
2
3
4
-100 -400kHz -200kHz 900MHz FREQUENCY 200kHz 400kHz
RF INPUT FREQUENCY - GHz
TPC 2. Input Sensitivity
TPC 5. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)
0
REF LEVEL = -14.3dBm
0
REF LEVEL = -10dBm
-10 -20 OUTPUT POWER - dB -30 -40 -50 -60 -70 -80 -90 -100 -2kHz -1kHz
OUTPUT POWER - dB
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 10
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 10
-93.0dBc/Hz
-84.0dBc/Hz
900MHz FREQUENCY
1kHz
2kHz
-2kHz
-1kHz
5800MHz FREQUENCY
1kHz
2kHz
TPC 3. Phase Noise (900 MHz, 200 kHz, and 20 kHz)
TPC 6. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz)
-6-
REV. A
ADF4106
-40 -50 -60 10dB/DIV RL = -40dBc/Hz RMS NOISE = 1.8 FIRST REFERENCE SPUR - dBc -5 -15 -25 -35 -45 -55 -65 -75 -85 -95 1MHz FREQUENCY OFFSET FROM 5800MHz CARRIER -105 0 1 2 3 TUNING VOLTAGE - V 4 5 VDD = 3V VP = 5V
PHASE NOISE - dBc/Hz
-70 -80 -90 -100 -110 -120 -130 -140 100Hz
TPC 7. Integrated Phase Noise (5.8 GHz, 1 MHz, and 100 kHz)
TPC 10. Reference Spurs vs. VTUNE (5.8 GHz, 1 MHz, and 100 kHz)
0
REF LEVEL = -10.0dBm
-120
-10 -20
OUTPUT POWER - dB
-30 -40 -50 -60 -70 -80 -90 -100 -2 -1
-66.0dBc
OUTPUT POWER - dBc/Hz
VDD = 3V, VP = 5V ICP = 5mA PDF FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 13 SECONDS AVERAGES = 1
VDD = 3V VP = 5V -130
-140
-150
-65.0dBc
-160
-170
5800 FREQUENCY - MHz
1
2
-180 10k
100k 1M 10M PHASE DETECTOR FREQUENCY - Hz
100M
TPC 8. Reference Spurs (5.8 GHz, 1 MHz, and 100 kHz)
TPC 11. Phase Noise (Referred to CP Output) vs. PFD Frequency
-60 VDD = 3V VP = 5V -70
10 9 8
PHASE NOISE - dBc/Hz
7
AIDD - mA
6 5 4 3
-80
-90 2 1 -100 -40 -20 0 20 40 TEMPERATURE - C 60 80 100 0 8/9 16/17 32/33 PRESCALER VALUE 64/65
TPC 9. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz) vs. Temperature
TPC 12. AIDD vs. Prescaler Value
REV. A
-7-
ADF4106
3.5 VDD = 3V VP = 3V
4 VP = 5V ICP = 5mA 2 6
3.0
2.5
DIDD - mA
ICP - mA 150 200 250 100 PRESCALER OUTPUT FREQUENCY 300
2.0
0
1.5
-2
1.0
-4
0.5 0 50
-6 0 0.5 1.0 1.5 2.0 2.5 3.0 VCP - V 3.5 4.0 4.5 5.0
TPC 13. DIDD vs. Prescaler Output Frequency
TPC 14. Charge Pump Output Characteristics
CIRCUIT DESCRIPTION REFERENCE INPUT SECTION
PRESCALER (P/P + 1)
The reference input stage is shown in Figure 2. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL
The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. There is a minimum divide ratio possible for fully contiguous output frequencies. This minimum is determined by P, the prescaler value, and is given by (P2 - P).
A AND B COUNTERS
NC REFIN
100k
SW2 NC SW1 TO R COUNTER BUFFER
NO
SW3 NC = NO CONNECT
The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with an RF input frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not.
Pulse Swallow Function
Figure 2. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 3. It is followed by a two-stage limiting amplifier to generate the CML clock levels needed for the prescaler.
BIAS GENERATOR 500 1.6V AVDD 500
The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is as follows:
fVCO P B A
RF A
IN
RF B
IN
fREFIN
fREFIN R Output frequency of external voltage controlled oscillator (VCO). Preset modulus of dual-modulus prescaler (8/9, 16/17, and so on). Preset divide ratio of binary 13-bit counter (3 to 8191). Preset divide ratio of binary 6-bit swallow counter (0 to 63). External reference frequency oscillator. fVCO = (P x B) + A x
[
]
AGND
Figure 3. RF Input Stage
-8-
REV. A
ADF4106
N = BP + A TO PFD
MUXOUT AND LOCK DETECT
13-BIT B COUNTER
FROM RF INPUT STAGE
PRESCALER P/P + 1 MODULUS CONTROL N DIVIDER
LOAD LOAD 6-BIT A COUNTER
The output multiplexer on the ADF4106 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Table V shows the full truth table. Figure 6 shows the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect is active high. When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. When lock has been detected, this output will be high with narrow lowgoing pulses.
DVDD
Figure 4. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
PHASE FREQUENCY DETECTOR AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse. See Table III.
VP CHARGE PUMP
ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT SDOUT MUX CONTROL MUXOUT
HI
D1
Q1 U1
UP
DGND
R DIVIDER
CLR1
Figure 6. MUXOUT Circuit
PROGRAMMABLE DELAY ABP2 ABP1 U3 CP
INPUT SHIFT REGISTER
HI
D2
Q2 U2
DOWN
N DIVIDER
CLR2
CPGND
The ADF4106 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table VI. Table I shows a summary of how the latches are programmed.
Table I. C2, C1 Truth Table
R DIVIDER
N DIVIDER
CP OUTPUT
Control Bits C2 C1 0 0 1 1 0 1 0 1
Data Latch R Counter N Counter (A and B) Function Latch (Including Prescaler) Initialization Latch
Figure 5. PFD Simplified Schematic and Timing (In Lock)
REV. A
-9-
ADF4106
Table II. Latch Summary
REFERENCE COUNTER LATCH
LOCK DETECT PRECISION
RESERVED
TEST MODE BITS
ANTIBACKLASH WIDTH
14-BIT REFERENCE COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (0) C1 (0)
N COUNTER LATCH
CP GAIN
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (0) C1 (1)
FUNCTION LATCH
FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PD POLARITY COUNTER RESET
POWERDOWN 2
PRESCALER VALUE
CURRENT SETTING 2
CURRENT SETTING 1
POWERDOWN 1
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 DB2 PD1 F1
DB1
DB0
C2 (1) C1 (0)
INITIALIZATION LATCH
FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PD POLARITY COUNTER RESET
POWERDOWN 2
PRESCALER VALUE
CURRENT SETTING 2
POWERDOWN 1
CURRENT SETTING 1
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 DB2 PD1 F1
DB1
DB0
C2 (1) C1 (1)
-10-
REV. A
ADF4106
Table III. Reference Counter Latch Map
LOCK DETECT PRECISION
RESERVED
TEST MODE BITS
ANTIBACKLASH WIDTH
14-BIT REFERENCE COUNTER
CONTROL BITS
DB23 DB22 X 0
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1
DB0
C2 (0) C1 (0)
X = DON'T CARE
R14 0 0 0 0 . . . 1 1 1 1 R13 0 0 0 0 . . . 1 1 1 1 R12 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... R3 0 0 0 1 . . . 1 1 1 1 R2 0 1 1 0 . . . 0 0 1 1 R1 1 0 1 0 . . . 0 1 0 1 DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383
ABP2 0 0 1 1
ABP1 0 1 0 1
ANTIBACKLASH PULSEWIDTH 2.9 ns 1.3 ns 6.0 ns 2.9 ns
TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION .
LDP 0 1
OPERATION THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15 ns MUST OCCUR BEFORE LOCK DETECT IS SET. FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15 ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION .
REV. A
-11-
ADF4106
Table IV. AB Counter Latch Map
CP GAIN CONTROL BITS RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
DB23 X
DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5
DB11 DB10 B4 B3
DB9 B2
DB8 B1
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1
DB0
C2 (0) C1 (1)
X = DON'T CARE
A6 0 0 0 0 . . . 1 1 1 1
A5 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
A2 0 0 1 1 . . . 0 0 1 1
A1 0 1 0 1 . . . 0 1 0 1
A COUNTER DIVIDE RATIO 0 1 2 3 . . . 60 61 62 63
B13 0 0 0 0 . . . 1 1 1 1
B12 0 0 0 0 . . . 1 1 1 1
B11 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 1 . . . 1 1 1 1
B2 0 0 1 1 . . . 0 0 1 1
B1 0 1 0 1 . . . 0 1 0 1
B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 8188 8189 8190 8191
F4 (FUNCTION LATCH) FASTLOCK ENABLE 0 0 1 1
CP GAIN 0 1 1 2 0 1 1
OPERATION CHARGE PUMP CURRENT SETTING IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING IIS PERMANENTLY USED. CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION
N = BP + A; P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N FREF), AT THE OUTPUT, NMIN, IS (P2 - P).
THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS.
-12-
REV. A
ADF4106
Table V. Function Latch Map
FASTLOCK ENABLE
FASTLOCK MODE
PD POLARITY
PRESCALER VALUE
CURRENT SETTING 2
CURRENT SETTING 1
COUNTER RESET DB2 F1
POWERDOWN 2
POWERDOWN 1
CP THREESTATE
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB1
DB0
C2 (1) C1 (0)
F2 0 1
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
F1 0 1
COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET
F3 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
F4 0 1 1
F5 X 0 1
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2
TC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
TC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
TC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
TC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63
M3 0 0 0 0 1 1 1 1
M2 0 0 1 1 0 0 1 1
M1 0 1 0 1 0 1 0 1
OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DV DVDD DD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND
CPI6 CPI3 0 0 0 0 1 1 1 1
CPI5 CPI2 0 0 1 1 0 0 1 1
CPI4 CPI1 0 1 0 1 0 1 0 1 3k 1.06 2.12 3.18 4.24 5.30 6.36 7.42 8.50
ICP (mA) 5.1 k 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 11 k 0.289 0.580 0.870 1.160 1.450 1.730 2.020 2.320
CE PIN 0 1 1 1 P2 0 0 1 1 P1 0 1 0 1
PD2 X X 0 1
PD1 X 0 1 1
MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN
PRESCALER VALUE 8/9 16/17 32/33 64/65
REV. A
-13-
ADF4106
Table VI. Initialization Latch Map
FASTLOCK ENABLE
FASTLOCK MODE
PD POLARITY
PRESCALER VALUE
CURRENT SETTING 2
CURRENT SETTING 1
COUNTER RESET
DB2 F1
POWERDOWN 2
POWERDOWN 1
CP THREESTATE
TIMER COUNTER CONTROL
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB1
DB0
C2 (1) C1 (1)
F2 0 1
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
F1 0 1
COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET
F3 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
F4 0 1 1
F5 X 0 1
FASTLOCK MODE FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2
TC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
TC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
TC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
TC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63
M3 0 0 0 0 1 1 1 1
M2 0 0 1 1 0 0 1 1
M1 0 1 0 1 0 1 0 1
OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DV DVDD DD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND
CPI6 CPI3 0 0 0 0 1 1 1 1
CPI5 CPI2 0 0 1 1 0 0 1 1
CPI4 CPI1 0 1 0 1 0 1 0 1 3k 1.06 2.12 3.18 4.24 5.30 6.36 7.42 8.50
ICP (mA) 5.1 k 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 11 k 0.289 0.580 0.870 1.160 1.450 1.730 2.020 2.320
CE PIN 0 1 1 1 P2 0 0 1 1 P1 0 1 0 1
PD2 X X 0 1
PD1 X 0 1 1
MODE ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN
PRESCALER VALUE 8/9 16/17 32/33 64/65
-14-
REV. A
ADF4106
FUNCTION LATCH Fastlock Mode 2
With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table V shows the input data format for programming the function latch.
Counter Reset
DB2 (F1) is the counter reset bit. When this is 1, the R counter and the A, B counters are reset. For normal operation, this bit should be 0. Upon power-up, the F1 bit needs to be disabled (set to 0). The N counter then resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle.)
Power-Down
The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4 through TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Table V for the timeout periods.
Timer Counter Control
DB3 (PD1) and DB21 (PD2) on the ADF4106 provide programmable power-down modes. They are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of PD2, PD1. In the programmed asynchronous powerdown, the device powers down immediately after latching a 1 into bit PD1, with the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device powerdown is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into bit PD1 (on condition that a 1 has also been loaded to PD2), the device will go into power-down on the occurrence of the next charge pump event. When a power-down is activated (either synchronous or asynchronous mode including CE pin-activated power-down), the following events occur: * All active dc current paths are removed. * The R, N, and timeout counters are forced to their load state conditions. * The charge pump is forced into three-state mode. * The digital lock detect circuitry is reset. * The RFIN input is debiased. * The reference input buffer circuitry is disabled. * The input register remains active and capable of loading and latching data.
MUXOUT Control
The user has the option of programming two charge pump currents. The intent is that the Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (e.g., when a new output frequency is programmed). The normal sequence of events is as follows. Users initially decide what the preferred charge pump currents will be. For example, they may choose 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2. At the same time, they must also decide how long they want the secondary current to stay active before reverting to the primary current. This is controlled by the timer counter control bits DB14 to DB11 (TC4 through TC1) in the function latch. The truth table is provided in Table V. When users want to program a new output frequency, they can simply program the AB counter latch with new values for A and B. At the same time, they can set the CP gain bit to a 1, which sets the charge pump with the value in CPI6 through CPI4 for a period of time determined by TC4 through TC1. When this time is up, the charge pump current reverts to the value set by CPI3 through CPI1. At the same time, the CP Gain bit in the AB counter latch is reset to 0 and is ready for the next time the user wants to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen when the fastlock mode bit (DB10) in the function latch is set to 1.
Charge Pump Currents
The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4106. Table V shows the truth table.
Fastlock Enable Bit
DB9 of the function latch is the fastlock enable bit. Only when this is 1 is fastlock enabled.
Fastlock Mode Bit
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is in Table V.
Prescaler Value
DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, Fastlock Mode 1 is selected, and if the fastlock mode bit is 1, Fastlock Mode 2 is selected.
Fastlock Mode 1
P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. Thus, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is not.
PD Polarity
The charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch.
This bit sets the phase detector polarity bit. See Table V.
CP Three-State
This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled.
REV. A
-15-
ADF4106
INITIALIZATION LATCH Counter Reset Method
When C2, C1 = 1, 1, the initialization latch is programmed. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). However, when the initialization latch is programmed, there is an additional internal reset pulse applied to the R and AB counters. This pulse ensures that the AB counter is at the load point when the AB counter data is latched, and the device will begin counting in close phase alignment. If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, so close phase alignment is maintained when counting resumes. When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, subsequent AB counter loads will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
* Apply VDD. * Do a function latch load (10 in 2 LSB). As part of this, load 1 to the F1 bit. This enables the counter reset. * Do an R counter load (00 in 2 LSB). * Do an AB counter load (01 in 2 LSB). * Do a function latch load (10 in 2 LSB). As part of this, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump but does not trigger synchronous power-down.
APPLICATION Local Oscillator for LMDS Base Station Transmitter
Figure 7 shows the ADF4106 being used with a VCO to produce the LO for an LMDS base station operation in the 5.4 GHz to 5.8 GHz band. The reference input signal is applied to the circuit at FREFIN and, in this case, is terminated in 50 . A typical base station system would have either a TCXO or an OCXO driving the reference input without any 50 termination. To have a channel spacing of 1 MHz at the output, the 10 MHz reference input must be divided by 10, using the on-chip reference divider of the ADF4106. The charge pump output of the ADF4106 (Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this example, the loop filter was designed so that the overall phase margin for the system would be 45 degrees. Other PLL system specifications are given below: KD = 2.5 mA KV = 80 MHz/V Loop Bandwidth = 50 kHz FREF = 1 MHz N = 5800 Extra Reference Spur Attenuation = 10 dB All of these specifications are needed and used to come up with the loop filter component values shown in Figure 7. Figure 7 gives a typical phase noise performance of -83 dBc/Hz at 1 kHz offset from the carrier. Spurs are better than -62 dBc. The loop filter output drives the VCO, which, in turn, is fed back to the RF input of the PLL synthesizer. It also drives the RF output terminal. A T-circuit configuration provides 50 matching between the VCO output, the RF output, and the RFIN terminal of the synthesizer. Note that the ADF4106 RF input looks like 50 at 5.8 GHz, so no terminating resistor is needed. When operating at lower frequencies, however, this is not the case. In a PLL system, it is important to know when the system is locked. In Figure 7, this is accomplished by using the MUXOUT signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer. One of these is the LD or (lock detect) signal.
After the device is initially powered up, there are three ways to program it.
Initialization Latch Method
* Apply VDD. * Program the initialization latch (11 in 2 LSB of input word). Make sure that F1 bit is programmed to 0. * Do a function latch load (10 in 2 LSB of the control word), making sure that the F1 bit is programmed to a 0. * Do an R load (00 in 2 LSB). * Do an AB load (01 in 2 LSB). When the initialization latch is loaded, the following occurs: 1. The function latch contents are loaded. 2. An internal pulse resets the R, A, B, and timeout counters to load state conditions and three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. 3. Latching the first AB counter data after the initialization word will activate the same internal reset pulse. Successive AB loads will not trigger the internal reset pulse unless there is another initialization.
CE Pin Method
* Apply VDD. * Bring CE low to put the device into power-down. This is an asynchronous power-down (it happens immediately). * Program the function latch (10). * Program the R counter latch (00). * Program the AB counter latch (01). * Bring CE high to take the device out of power-down. The R and AB counters will then resume counting in close alignment. Note that after CE goes high, a duration of 1 s may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after VDD was initially applied.
-16-
REV. A
ADF4106
VDD VP RFOUT
100pF 100pF VCC 20pF 18 18
1000pF FREFIN 51
1000pF
AVDD DVDD VP CP REFIN 100pF
6.2k
4.3k
V940ME03
18
ADF4106
1.5nF CE MUXOUT CLK DATA LE RFINA RSET LOCK DETECT 1, 3, 4, 5, 7, 8, 9, 11, 12, 13
SPI COMPATIBLE SERIAL BUS
100pF
CPGND
RFINB
AGND
5.1k
DGND
100pF NOTE DECOUPLING CAPACITORS (0.1 F/10pF) ON AVDD, DVDD, VP OF THE ADF4106 AND ON VCC OF THE V940ME03 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 7. Local Oscillator for LMDS Station
INTERFACING
The ADF4106 has a simple SPI compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (latch enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of SCLK get transferred to the appropriate latch. See Figure 1 for the timing diagram and Table I for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 s. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds.
ADuC812 Interface
(R)
On first application of power to the ADF4106, three writes are needed (one to the R counter latch, one to the N counter latch, and one to the function latch) for the output to become active. I/O port lines on the ADuC812 are also used to control power-down (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz.
SCLOCK MOSI CLK DATA LE CE MUXOUT (LOCK DETECT)
Figure 8 shows the interface between the ADF4106 and the ADuC812 MicroConverter(R). Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4106 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer.
ADuC812
I/O PORTS
ADF4106
Figure 8. ADuC812 to ADF4106 Interface
REV. A
-17-
ADF4106
ADSP-2181 Interface
Figure 9 shows the interface between the ADF4106 and the ADSP-21xx digital signal processor. The ADF4106 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
SCLOCK MOSI
CLK DATA LE CE
ADSP-21xx
TFS
ADF4106
I/O FLAGS MUXOUT (LOCK DETECT)
Figure 9. ADSP-21xx to ADF4106 Interface
-18-
REV. A
ADF4106
OUTLINE DIMENSIONS
16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MS-153AB
20-Lead Lead Frame Chip Scale Package [LFCSP] (CP-20)
Dimensions shown in millimeters
4.0 BSC SQ 0.60 MAX PIN 1 INDICATOR
TOP VIEW
0.60 MAX
16 15
20 1
3.75 BSC SQ 0.75 0.55 0.35
11 10
BOTTOM VIEW
6 5
2.25 2.10 SQ 1.95
12 MAX 1.00 0.90 0.80 SEATING PLANE 0.50 BSC
0.80 MAX 0.65 NOM 0.05 0.02 0.00
0.30 0.23 0.18 COPLANARITY 0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
REV. A
-19-
ADF4106 Revision History
Location 5/03--Data Sheet changed from REV. 0 to REV. A. Page
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Update OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
C02720-0-5/03(A)
Edits to TPC 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
-20-
REV. A

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